In general, a thin film transistor typically is used in place of a load resistor in SRAMs of 1 mega-bit or higher densities and also is widely used as a switching element for switching image data signals of pixel regions in a liquid crystal display. In order to obtain a high quality SRAM, it is necessary to decrease the power consumption and improve the memory characteristics by decreasing the off current and increasing the on current of thin film transistors. Accordingly, research has been conducted towards improving the on/off current ratio.
A conventional method for fabricating a thin film transistor to improve the on/off current ratio based on above principle is to be explained hereinafter, referring to the attached drawings. FIGS. 1A to 1D are sectional drawings illustrating processes for fabricating a conventional thin film transistor, in which the fabrication of the MOS thin film transistor utilizes a bigger grain size by a solid state grain growth of body polysilicon based on a bottom gate. The solid state grain growth in this case is achieved by a heat treatment for a long time (about 24 hours) at a temperature of about 600.degree. C.
As illustrated in FIG. 1A, polysilicon is deposited on insulation substrate 1 (or an insulation film), and the polysilicon is subjected to a patterning with a photo etching process using a gate mask, forming gate electrode 2. As illustrated in FIG. 1B, gate insulation film 3 and body polysilicon 4 are deposited successively with chemical vapor deposition (CVD) methods on the overall surface thereof. Thereafter, the grain size of the body polysilicon is grown bigger through a solid state grain growth method of heat treating for a long time (about 24 hours) at a temperature of about 600.degree. C.
As illustrated in FIG. 1C, photosensitive film 5 is deposited on polysilicon 4 and is subjected to an exposure and a development process, thereby masking a channel region. The masking of the channel region is carried out for source region 6a to overlap with gate electrode 2 and for drain region 6b to off-set gate electrode 2.
As illustrated in FIGS. 1C and 1D, p type impurities (BF.sub.2) are injected into exposed body polysilicon 4 forming source region 6a and drain region 6b, completing fabrication of a conventional p type MOS thin film transistor. The letters a, b, c and d in FIG. 1D indicate a source region, a channel region, an offset region and a drain region, respectively.
Such a conventional method for fabricating a thin film transistor has following problems.
First, because the channel region as well as the offset region are defined with a photomask process at the same time, which is a complicated process, hard to reproduce and seriously varies the off current depending on the degree of alignment, the reliability of the thin film transistor becomes lower.
Second, as the channel of the thin film transistor is constructed in a planar manner, as the cell size becomes smaller the length of the channel becomes shorter, which may result in an increase in leakage current, and it is difficult to achieve high integration.